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2020-11-20 18:39:12 × raehik quits (~raehik@cpc95906-rdng25-2-0-cust156.15-3.cable.virginm.net) (Ping timeout: 256 seconds)
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2020-11-20 18:53:00 <int-e> https://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made hmm. interesting niche: turn working FPGAs into ASICs that have an FPGA-like fabric in the bottom layers, thereby saving on mask costs
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2020-11-20 19:01:50 <electricityZZZZ> right,... i'm saying that today, this might become more valuable than historically,...
2020-11-20 19:02:03 <electricityZZZZ> there also is https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices.html
2020-11-20 19:02:40 <electricityZZZZ> cloud services mean that if you make a special chip you can make it available to everybody pretty easily,...
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2020-11-20 19:03:36 <geekosaur> but every time you turn around they come up with faster or more capable but more expensive fab, and people want to use that more capable
2020-11-20 19:03:58 <davean> electricityZZZZ: You can do cheap fabrication on old nodes - its common to do that. Its just that for computation its not useful.
2020-11-20 19:04:09 <electricityZZZZ> well it's a competition between what you can do in software on a CPU today and those gains
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2020-11-20 19:04:25 <electricityZZZZ> vs an FPGA or an ASIC (fabricated on an old node, at least to begin with)
2020-11-20 19:04:32 <davean> electricityZZZZ: so they're used for non-computational things usually, or microcontrolers, etc.
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2020-11-20 19:05:54 <electricityZZZZ> furthermore if your software can be programmed so that the process from CPU all the way to ASIC was smooth, that would be pretty great
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2020-11-20 19:11:54 <davean> electricityZZZZ: I find your tautology compelling.
2020-11-20 19:12:53 <electricityZZZZ> what are you referring to when you say my tautology
2020-11-20 19:13:00 <electricityZZZZ> the "smooth process from CPU to ASIC"?
2020-11-20 19:14:07 <davean> yes
2020-11-20 19:14:16 <electricityZZZZ> yeah
2020-11-20 19:14:42 <electricityZZZZ> furthermore, the ASIC aspect of things can help with revenue models
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2020-11-20 19:16:01 × hlisp quits (~hlisp@114.246.35.11) (Ping timeout: 260 seconds)
2020-11-20 19:16:21 <int-e> ASIC for computation... I guess the famous examples where this has been done are ASIC bitcoin miners (sigh...) and Google's TPUs?
2020-11-20 19:16:41 <electricityZZZZ> yeah but wouldn't redis-as-an-ASIC make sense?
2020-11-20 19:16:59 <int-e> no
2020-11-20 19:17:07 <davean> int-e: thats the famous example vs. like network controllers?
2020-11-20 19:17:12 <int-e> too specific, and it's memory
2020-11-20 19:17:25 <electricityZZZZ> there might also be security advantages to having a firewall etched into an ASIC
2020-11-20 19:17:27 <int-e> davean: do those count as computation?
2020-11-20 19:17:29 <davean> electricityZZZZ: also a lot of NVMe drives?
2020-11-20 19:18:31 <davean> int-e: They run offload, application specific offload, packet routing, delivery, firewalls, etc? Its how we can manage multi 100Gb connections usefully to single systems and VMs.
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2020-11-20 19:18:43 <davean> They run bytecode interpriters
2020-11-20 19:18:46 <electricityZZZZ> davean: are you saying that NVMe drives already have hardware key-value stores onboard?
2020-11-20 19:19:03 <davean> electricityZZZZ: No, but thats true. What I'm saying is higher end NVMe drives are run by FPGAs.
2020-11-20 19:19:05 luke is now known as Guest69432
2020-11-20 19:19:36 <electricityZZZZ> davean: yeah so that's "equivalent to an ASIC", mostly
2020-11-20 19:19:47 <davean> what?
2020-11-20 19:20:22 <int-e> FPGAs have a far lower one-time cost. That's basically their point.
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2020-11-20 19:20:57 <davean> int-e: no, also reprogrammability. Which is why you see them in any non-low-end NIC
2020-11-20 19:21:04 <electricityZZZZ> i'm saying perhaps your FPGA-on-NVMe device sufficienly covers more efficient CPU offloading to the point that it isn't worth moving to ASIC in many/most applications
2020-11-20 19:21:10 <int-e> davean: Obviously there are tons of ASICs around. They are cheap *if* you buy them in the 100s of thousands or millions.
2020-11-20 19:21:13 <davean> Its not FPGA-on-NVMe
2020-11-20 19:21:30 <davean> Its FPGA-is-what-makes-it-NVMe
2020-11-20 19:21:36 <electricityZZZZ> oh wow really?
2020-11-20 19:21:52 <davean> int-e: Except they're not flexable.
2020-11-20 19:22:04 <davean> int-e: so their cheapness is moot in a lot of applications - like NICs
2020-11-20 19:22:05 <int-e> (And I do distinguish between FPGAs and ASICs)
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2020-11-20 19:22:34 <int-e> davean: I don't disagree.
2020-11-20 19:23:14 <electricityZZZZ> davean: but you said the FPGA applies to high end NVMe (i.e. lower end NVMe drives don't have the FPGA), so what you are saying isn't self-consistent
2020-11-20 19:23:29 <davean> No, it is, I think you're just lost.
2020-11-20 19:23:42 <davean> There has to be a controller to turn flash into NVMe
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2020-11-20 19:24:03 <davean> that controller on lower end devices is a small CPU. On higher end devices its a medium size FPGA.
2020-11-20 19:24:08 <electricityZZZZ> but my application doesn't distribute its program to that controller
2020-11-20 19:24:20 <davean> Some do
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2020-11-20 19:25:25 <davean> And the POINT of smartnics, etc is specificly to bake stuff the OS would be doing in software into the data plane of the NIC.
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2020-11-20 19:26:45 <electricityZZZZ> yeah,...
2020-11-20 19:26:52 <davean> And some NVMe is run as a KV store
2020-11-20 19:26:55 <davean> also some HDs
2020-11-20 19:27:04 <davean> there are NVMe modes
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2020-11-20 19:27:35 <electricityZZZZ> ...and i guess some intel CPUs are going to be shipping with integrated FPGAs. ... shouldn't we have a way of programming that in a productive manner? that would be sort of the first step in this logical chain
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